Gabriel Galeote-Checa

Gabriel Galeote-Checa

Senior Signal Processing & Algorithms Engineer, Ph.D. — Seville, Spain

Resume

About Me

Digital Signal Processing engineer and Ph.D. specializing in RTL/ASIC digital design, FPGA architectures, and quantized, compute-in-memory (CIM) algorithms for real-time bioelectronics, neural implants, and ECG signal processing.

Research Interests

My work sits at the crossroads of hardware–software co-design, signal processing, and medical devices. I take algorithms from Python/PyTorch prototypes through RTL (Verilog/VHDL) to synthesized, verified silicon, with a focus on quantization and compute-in-memory techniques for low-power, real-time inference on constrained platforms.

Current Research

In March 2026, I completed my Ph.D. in Physical Sciences and Technology (Microelectronics) at the Instituto de Microelectrónica de Sevilla, Spain. My doctoral research covered end-to-end RTL architecture design, quantized compute-in-memory (CIM) algorithms for large-scale multichannel systems (up to 1024 simultaneous channels), and hardware for the detection and pattern recognition of epileptic seizures.

This research culminated in the successful synthesis and fabrication of a seizure detection system-on-chip utilizing SkyWater 130nm and IHP 180nm processes, as well as tape-outs leveraging TSMC 65nm low-power and 180nm technologies.

Academic Contributions

My scholarly contributions include 4 journal articles and 5 conference papers. I have served for more than three years as an international reviewer for IEEE conferences and high-impact journals. I am a member of the IEEE.

Technical Skills

Hardware Description & RTL

  • Verilog / SystemVerilog
  • VHDL
  • Cocotb (Python verification)
  • RTL-to-GDS: Librelane / OpenLane
  • Cadence Genus & Virtuoso
  • Xilinx Vivado & Vitis

Process Nodes & Tapeouts

  • SkyWater 130nm
  • IHP 130nm / 180nm
  • TSMC 65nm (LP) & 180nm
  • Tiny Tapeout program (multiple shuttles)
  • Zynq-7020 SoC / FPGA

Algorithms & Machine Learning

  • Quantized & compute-in-memory (CIM) inference
  • Digital signal processing (filters, spectral analysis)
  • Spike / seizure detection, time-series segmentation
  • Python, PyTorch, NumPy/SciPy
  • C / C++ for embedded inference

Embedded & Firmware

  • ARM Cortex-M0/M4/M7/M33
  • STM32, NRF9620
  • RTOS
  • Pytest, Jenkins, GitLab CI

Analog, PCB & RF

  • KiCad, EAGLE
  • HFSS, COMSOL
  • Wireless power transfer / RF design
  • Flexible & stretchable circuit fabrication

Regulatory & Compliance

  • FDA submissions
  • IEC 60601-2-47/25
  • ISO 9001

Experience

Analog Devices Inc.

Senior Signal Processing and Algorithms Engineer (Medical Products) — – Present

Digital Healthcare division, Norwood, MA / Madrid, Spain.

  • Development, training, quantization, and deployment of Machine Learning models optimized for constrained medical devices, bridging pathology detection and strict power/memory limits of edge computing.
  • Architecting algorithms for real-time cardiac pathology detection on STM32 and NRF9620 microcontrollers, focusing on efficient computing and reduced power consumption.
  • Technical support for FDA submissions (IEC 60601-2-47/25), translating complex algorithmic performance into regulatory-grade documentation.
  • Representing the company at international congresses and technical conferences through writing and dissemination of scientific papers.
Python C/C++ DSP Quantization ARM Cortex-M ECG Machine Learning

Analog Devices Inc.

Signal Processing and Algorithms Engineer — –

Digital Healthcare division, Norwood, MA / Valencia, Spain.

  • Development of signal processing algorithms and architectures for diagnosis of pathologies in ECG signals for on-device ambulatory monitoring devices.
  • Conceptualization, design, development, and integration of algorithms on ECG medical devices for low-power critical applications. Implementation of signal conditioning and curation steps for machine learning algorithms on high-performance cloud computing.
  • Analysis of product requirements and specifications in compliance with IEC/ISO medical device regulations and standards for FDA submissions. Compliance with IEC60601 and ISO9001.
  • Implementation of software best practices and tests for CI/CD using Jenkins, GitLab, and pytest.
  • Implementation of high-performance algorithms for embedded microcontrollers using ARM Cortex-M4, Cortex-M7, and Cortex-M33.
Python C/C++ DSP ARM Cortex-M ECG CI/CD Jenkins Machine Learning

Analog Devices Inc.

Systems Applications Engineer — –

Valencia, Spain.

  • Designed and developed firmware verification tests and analyzed electronic schematics and layouts.
  • Built and maintained hardware test benches for automated firmware verification using Pytest, GitLab CI, and Jenkins.
  • Managed project tracking and reports using Agile methodologies (Jira, Scrum) and RTOS on ARM Cortex-M4.
Firmware RTOS ARM Cortex-M4 Jira GitLab CI

Imperial College London

Visiting Researcher — –

Next Generation Neural Interfaces (NGNI) Laboratory, London, U.K.

  • Design, synthesis, RTL analysis, and verification of algorithm IPs in Cadence Virtuoso, Genus, and Xilinx Vivado, Vitis.
  • Collaborated on the design of neural interfaces and implantable systems.
Cadence VHDL Verilog FPGA RTL

Instituto de Microelectrónica de Sevilla

Researcher (Neuromorphic Computing Group) — –

Seville, Spain.

  • Conducted research tasks for the HERMES FET-PROACT European project, designing and testing ICs for brain bioimplantable devices.
  • Designed digital signal processing architectures (Python/C++) for microelectrode arrays used for intracortical EEG using DSP processors and FPGAs.
  • Mixed-signal IC design in VHDL and Verilog. Full system implementation from DMA I/O routines, algorithm implementation, RTL analysis and laboratory testing.
  • Digital design flow and top-level system integration for FPGAs. Used Zynq 7020 SoC for FPGA Verilog code verification and functional test preparation.
Python C/C++ VHDL Verilog FPGA Zynq 7020 MEA

Polytechnic University of Madrid

Research Assistant — –

Madrid, Spain.

  • Management of European project proposal documentation and design of electronic schematics. Managed specific work packages of >1M€ projects.
  • Developed IoT and WoT architectures on STM32 Cortex-M4 and Raspberry Pi.
IoT STM32 Raspberry Pi Project Management

University of Glasgow

Research Scholar (Microelectronics Lab — MeLab) — –

Glasgow, United Kingdom.

  • Designed and fabricated a bioelectronic brain implantable device for treating epilepsy for the FET-Proact HERMES European project.
  • Published two conference papers (ICECS 2019 and ISCAS 2021) and one journal paper (Advanced Science).
  • Designed RF electromagnetic wireless power transfer systems using HFSS and EAGLE.
  • Fabricated flexible and stretchable circuits on DuPont Pyralux AP8535R using automatic PCB printing with Voltera machine.
PCB Design HFSS EAGLE RF Bioelectronics Flexible Circuits

Education

Instituto de Microelectrónica de Sevilla

Ph.D. in Physical Sciences and Technology, Microelectronics — –

Neuromorphic Computing Group, Seville, Spain.
  • Design, implementation and verification of mixed-signal algorithms for neural implantable technologies.
  • End-to-end implementation from requirements and architecture, through proof of concept (Python, C/C++), to VHDL/Verilog implementation, validation, and verification on FPGA and RTL analysis.
  • Used Cadence (Genus and Virtuoso) and Xilinx (Vivado and Vitis) for analog and digital design.
  • Research stay at Next Generation Neural Interfaces (NGNI) Laboratory at Imperial College London.

University of Glasgow

MSc in Mechatronics, Electronics Engineering — –

Glasgow, Scotland.
  • Relevant Coursework: Real-time embedded systems programming (C++), Digital Signal Processing (DSP), Control and Systems engineering.

Incheon National University

International Scholarship (GPA: 4.00 / 4.00) — –

Incheon, South Korea.
  • Relevant Coursework: Brain engineering, nanodevice engineering and nanoengineering.

Universidad de Málaga

Bachelor of Science in Biomedical Engineering (GPA: 3.23 / 4.00) — –

Malaga, Spain.
  • Relevant Coursework: Electronic Design, Data Structures and Algorithms (Java/C++), Digital Signal Processing (Matlab/Python), Biomaterials, Bioimplants, Bioinstrumentation.

Publications

You can also find my articles on Google Scholar and ORCID.

Journal Articles

  1. Galeote-Checa, G., Panuccio, G., Linares-Barranco, B., & Serrano-Gotarredona, T. (2026). Hardware Implementation of a Real-Time Adaptive Time-Series Segmentation Algorithm for Intracortical Implants. IEEE Transactions on Biomedical Circuits and Systems. DOI
  2. Galeote-Checa, G., Panuccio, G., Canal-Alonso, A., Linares-Barranco, B., & Serrano-Gotarredona, T. (2025). Time series segmentation for recognition of epileptiform patterns recorded via microelectrode arrays in vitro. PLOS ONE, 20(1), e0309550. DOI
  3. McGlynn, E., Nabaei, V., Ren, E., Galeote-Checa, G., Das, R., Curia, G., Heidari, H. (2021). The Future of Neuroscience: Flexible and Wireless Implantable Neural Electronics. Advanced Science, 8, 2002693. DOI
  4. Galeote-Checa, G. (2018). ECG analógico controlado por Arduino para monitorizar parámetros cardíacos. Universidad de Málaga.

Conference Papers

  1. Galeote-Checa, G. (2025, July). ECG Signal Quality Assessment for QRS detectability in Single-Lead On-Device Processing. In 47th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).
  2. Galeote-Checa, G., Gotarredona, T. S., Panuccio, G., & Linares-Barranco, B. (2025, May). Real-Time Seizure Detection in Microelectrode Array based on Z-Test Spike Detection for Hardware Implementation. In 2025 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-5). IEEE.
  3. Galeote-Checa, G., Panuccio, G., Linares-Barranco, B., & Serrano-Gotarredona, T. (2021). Baseline Features Extraction from Microelectrode Array Recordings in an in vitro model of Acute Seizures using Digital Signal Processing for Electronic Implementation. IEEE International Conference on Omni-Layer Intelligent Systems (COINS), pp. 1-6. DOI
  4. Galeote-Checa, G., Nabaei, V., Das, R., & Heidari, H. (2020). Wirelessly Powered and Modular Flexible Implantable Device. In 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Glasgow, Scotland.
  5. Galeote Checa, G., Kaya, U., Sohail, L., Das, R., & Heidari, H. (2019). Flexible Wirelessly Powered Implantable Device. 26th IEEE International Conference on Electronics Circuits and Systems (ICECS). DOI

Other Publications

  1. Galeote-Checa, G. (2019). Una nueva especie llamada 'homo tecnologicus': Biohackers y cíborgs: la revolución tecnológica de nuestra era. Telos: Cuadernos de comunicación e innovación, vol. 110, pp. 97-101.
  2. Galeote-Checa, G. (2018). Ciborg: Analisis actual y futuras consecuencias. Ariel-Revista de filosofía, 22, 23-29.
  3. Galeote Checa, G. & Pimentel Naranjo, V. (2016). Quantum Dots. PIE15-110: Jornadas de Enseñanza Multidisciplinar de la Biotecnología y de las Ciencias Ómicas. Universidad de Málaga.

Projects

RTL, ASIC & FPGA

FIR Filter — Adder Tree

Neural Time-Series Segmentation

Non-Linear Signal Operators

Portable ECG with Arduino

Stress Controller

Brain Implantable Device

Tiny Tapeout & CORDIC Hardware

ZdensityRODE — Seizure Classifier ASIC

RTL hardening of a real-time ictal / interictal / baseline event classifier on the Tiny Tapeout program, submitted across multiple shuttles & process nodes: SkyWater 130nm and IHP 130/180nm. Multi-channel architecture with on-chip RAM buffering and per-channel spike/event flagging.

Verilog Tiny Tapeout SkyWater 130nm IHP Seizure Detection
View on GitHub →

CORDIC Core

Hardware-verified Verilog implementations of the CORDIC algorithm: a circular core for sine/cosine (rotation mode) and a hyperbolic core for fixed-point square roots (vectoring mode), with a normalization wrapper and AXI-friendly top-level IP — multiplier-free, using only shifts and adds.

Verilog CORDIC Fixed-Point Cocotb Jupyter
View on GitHub →

Neural Mass Model of Epilepsy

Python simulation environment for neural mass models used to study the generation of epileptiform activity, supporting algorithm validation ahead of hardware implementation for seizure-detection ASICs.

Python Neural Mass Models Epilepsy Simulation
View on GitHub →

Signal Processing & Algorithms

Classic Filter Design in Python

Reference implementations and design notebooks for classic FIR and IIR digital filters — coefficient design, frequency response analysis, and quantization effects for later RTL porting.

Python FIR IIR DSP
View on GitHub →

Digital Signal Processing Laboratory

Coursework and lab exercises from the University of Glasgow's DSP module — sampling, spectral analysis, and filter design implemented and verified in Python.

Python DSP Coursework
View on GitHub →

FPGA Benchmark

A set of benchmark designs, notes, and worked examples in VHDL for exploring FPGA architecture, timing, and resource utilization trade-offs.

VHDL FPGA Benchmarking
View on GitHub →

Embedded Systems & IoT

STM32L475VG HTTP Server

Bare-metal HTTP server implementation for the STM32L475VG IoT discovery node, exposing sensor data over a lightweight web interface.

C STM32 IoT HTTP
View on GitHub →

Contact